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Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications [electronic resource] / by Taimur Rabuske, Jorge Fernandes.

By: Contributor(s): Material type: TextSeries: Analog Circuits and Signal ProcessingPublisher: Cham : Springer International Publishing : Imprint: Springer, 2017Description: XI, 165 p. 98 illus., 46 illus. in color. online resourceContent type:
  • text
Media type:
  • computer
Carrier type:
  • online resource
ISBN:
  • 9783319396248
Subject(s): Additional physical formats: Printed edition:: No titleDDC classification:
  • 621.3815 23
Online resources:
Contents:
Introduction -- ADCs for Low Voltage Low Power Applications -- Review of SAR ADC Switching Schemes -- Analysis of the charge sharing SAR ADC topology -- Techniques for Low Voltage Low Power CS SAR ADCs -- Noise-aware comparator optimization -- CS ADCs with MOSCAP-based DACs -- Design and Implementation of two Low-Voltage SAR ADCs -- Conclusion.
In: Springer eBooksSummary: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
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Introduction -- ADCs for Low Voltage Low Power Applications -- Review of SAR ADC Switching Schemes -- Analysis of the charge sharing SAR ADC topology -- Techniques for Low Voltage Low Power CS SAR ADCs -- Noise-aware comparator optimization -- CS ADCs with MOSCAP-based DACs -- Design and Implementation of two Low-Voltage SAR ADCs -- Conclusion.

This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.